Due to their fast switching times and high current densities, fin field effect transistor (FinFET) devices are of a desired device architecture. In its basic form, a FinFET device includes a source, a drain and one or more fin-shaped channels between the source and the drain. A gate electrode over the fin(s) regulates electron flow between the source and the drain.
The architecture of a FinFET device, however, presents notable fabrication challenges. For example, as feature sizes of the devices get increasingly smaller (commensurate with current technology) accurately and consistently contacting the source and drain becomes a problem. Some previous demonstrations of FinFET devices have been on single fins, isolated devices or devices built at a greatly relaxed pitch. These characteristics allow the problem of contacting the source and drain to be sidestepped.
Source/drain landing pads are sometimes used to contact the fins, which provides mechanical stability during processing, simplifies the device contacting scheme and reduces external resistance. However, the landing pads have to be precisely aligned with the gate in order to achieve a practical gate pitch (in the case of logic layouts using minimum gate pitch) and to minimize variations in extrinsic resistance and parasitic capacitance. Properly and consistently aligning the landing pads with the gate is difficult. As a result, alternate contacting schemes that do not use landing pads have been proposed. Without landing pads however, contact has to be made with individual fins, which can be difficult, e.g., due to mismatches between minimum fin pitch and minimum pitch for contact vias.
Solutions such as epitaxially merged fins or use of contact bars to contact multiple fins have also been proposed. For example, epitaxial raised source and drain regions are used to reduce series resistance and simplify the contacting scheme. See, for example, Kaneko et al., Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15 nm finfet with elevated source/drain extension, IEDM Technical Digest, pgs. 844-847 (2005), Kavalieros et al., Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering, Symposium on VLSI Technology 2006, pgs. 50-51 (2006) and Shang et al., Investigation of FinFET Devices for 32 nm Technologies and Beyond, Symposium on VLSI Technology 2006, pgs. 54-55 (2006).
Epitaxial processes, however, have drawbacks due to their extreme sensitivity to surface chemistry, crystal orientation and growth conditions. For example, with an epitaxial growth process, parasitic growth on the gate has to be prevented, the rest of the device structure has to be protected from aggressive pre-epitaxial cleans and the faceting and direction of epitaxial growth has to be controlled to minimize both parasitic capacitance and resistance and to achieve similar growth on differently doped source and drain surfaces.
Scaling fin width is another challenge for FinFET manufacturing. For schemes where the fins are formed before gate patterning, thin fins must survive gate and spacer processing, which often involves aggressive etching processes.
U.S. Patent Application Publication No. 2006/0189043 filed by Schulz (hereinafter “Schulz”) describes a finFET device fabrication method involving use of a mask layer over a substrate, creating a trench in the mask layer, forming fins in the substrate within the trench and then forming a planarized gate electrode in the trench over the fins. The teachings of Schulz, however, do not provide for formation of fins with the precision and consistency needed for manufacture, especially in the context of scaled process technology.
Therefore, FinFET devices and methods for fabrication thereof that improve the device contacting scheme and scalability of the devices would be desirable